A DAC accepts an N-bit digital input signal, and ideally produces 2.sup.N analog output signals uniformly spaced in time. While DACs can be implemented to produce either a voltage or current output signal, a DAC which produces a current output signal has been conceptually easier to implement. Current output DACs are typically implemented with an array of switches, and either a binary weighted array of current sources or unit current sources. The accuracy of the resulting DAC depends on how accurately the individual current sources can be matched. With a careful layout, device matching suitable for 10-bit accuracy can be expected. To obtain higher resolutions, special design techniques are required.
One of the earliest techniques for increasing the accuracy of a DAC is described in "An Inherently Monotonic 12 bit DAC", by J. A. Schoeff, IEEE Journal of Solid State Circuits, Vol SC-14, No 6, pp 904-911, December 1979, which uses a "segmented" approach. An N+M bit segmented DAC uses an M-bit binary weighted DAC for the least significant bits and 2.sup.N unit current sources for the most significant bits of an input signal. One of the unit current sources is used to feed the binary weighted DAC. This ensures that the range of the binary weighted DAC is equal to one unit current source. By switching the unit current sources to the binary weighted DAC or directly to the output, depending on the input code, a high resolution monotonic DAC is stated to be achieved.
However, a problem with this approach is that the unit current sources are not perfectly matched. These mismatches lead the DAC to display an integral non-linearity at DC, and harmonic distortion for time varying signals.
A method of circumventing the problem of mismatched unit current sources in a segmented DAC is described in "A Low-Power Stereo 16-bit CMOS D/A converter for Digital Audio", by H. J. Schouwenaars et al, IEEE Journal of Solid State Circuits, Vol SC-23, No 6, pp.1290-1297, December 1988. The authors propose that the outputs of the unit current sources should be averaged. This requires that the outputs of the unit current source array should be switched between the binary weighted DAC and the direct output during each output period. The switching is done in a manner so that the direct output and the binary weighted DAC each see the average of the currents provided by the unit current sources.
While this approach increases the linearity of the circuit, the unit sources must be switched faster than the output of the DAC, thereby reducing the maximum speed of operation of the DAC. In addition, sizeable off-chip capacitors are required to filter the ripple caused by the switching.
A completely different approach to achieving high linearity in a DAC which is based on an array of unit elements, is based on data weighted averaging (DWA), described by O. Nys et al in "A 19-bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging", IEEE Journal of Solid State Circuits, Vol. SC-32, No.7, pp.933-942, July 1997. DWA uses an array of unit current sources (or capacitors) each of which can be driven separately.
Like a traditional DAC based on unit current sources, the appropriate number of elements in the array is switched to the output for each input code. Unlike traditional DACs, in which the same code will cause the same elements to be switched to the output, the elements that are switched to the output in a DWA DAC are dependent on the previous inputs. In particular, the elements are used sequentially in such manner that all elements are used in the array before starting at the beginning of the sequence again.
This approach has two benefits: firstly that the errors in the unit current sources are converted from linearity errors to noise. This has the effect of linearizing the DAC. In addition, the resulting noise is not white noise. Instead, the noise displays what is called first order noise shaping which yields a 9 dB improvement in in-band noise for each doubling of the sampling rate of the DAC. Hence, a relatively low over-sampling ratio is required to significantly improve the in-band signal-to-noise ratio and linearity of a DAC.
The second benefit is the simplicity of the transformation algorithm. The algorithm simply has to keep track of the last element used in the array, and is implemented with what is called a "cycle counter".
The primary problems with DWA for high resolution DACs are the large number of unit devices that are required to be used, and the large cycle counter, both of which consume a large integrated chip area.